general description the max2106 low-cost, direct-conversion tuner ic isdesigned for use in digital direct-broadcast satellite (dbs) television set-top box units and is a pin-for-pin upgrade for the max2104. its direct-conversion archi- tecture reduces system cost compared to devices with if-based architectures. the max2106 directly tunes l- band signals to baseband using a broadband i/q downconverter. the operating frequency range spans 925mhz to 2175mhz. the ic includes a low-noise amplifier (lna) with gain control, i and q downconverting mixers, lowpass filters with gain and frequency control, a local oscillator (lo) buffer with a 90 quadrature network, and a charge- pump-based phase-locked loop (pll) for frequency control. the max2106 has an on-chip lo, requiring only an external varactor-tuned lc tank for operation. the lo? output drives the internal quadrature genera- tor and has a buffer amplifier to drive off-chip circuitry. the max2106 comes in a 48-pin thin quad flat-pack package with exposed paddle (ep). applications advantages over max2104 ? improved front end achieves 10.2db nf at 1550mhz ? higher input iip3: 11.5dbm at 1550mhz ? reduced spurious downconversion products ? capable of using an external synthesizer features ? drop-in replacement for max2104 designs requires only minor software upgrade and two external resistor value changes ? complete low-cost solution for dbs directdownconversion ? high level of integration minimizes componentcount ? 1mbaud to 45mbaud operation ? selectable lo buffer ? +5v single-supply operation ? 925mhz to 2175mhz input frequency range ? on-chip quadrature generator, dual-modulusprescaler (/32, /33) ? on-chip crystal oscillator amplifier ? pll phase detector with gain-controlled chargepump ? input levels: -25dbm to -68dbm per carrier ? over 50db gain control range ? noise figure = 10.2db; iip3 = +11.5dbm (at 1550mhz) ? automatic baseband offset correction max2106 dbs direct downconverter ________________________________________________________________ maxim integrated products 1 19-1627; rev 3; 6/05 functional diagram appears at end of data sheet. ordering information pin configuration *ep = exposed paddle. + denotes lead-free package. pllin-pllin+ mod- mod+ lodivsel iout+ iout- v cc qout+qout- rfband flclk v cc cflt xtl- xtl+ gnd v cc rfin- rfin+ gndgnd qdc- qdc+ 12 3 4 5 6 7 8 9 1011 12 1314 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 3635 34 33 32 31 30 29 28 27 26 25 idc- idc+ lobufsel gnd rfout cpg1 v cc xtlout cpg2 gc1gc2 insel cpfb gnd v cc tank+vrlo tank- gnd gnd v cc lobuf-/tpsout-lobuf+/fpsout+ tqfp max2106 top view u.s. dss set-top receiverseuropean dvb-compliant systems cellular base stations wireless local loop broadband systemslmds professional receivers vsat microwave links for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max2106ucm 0 c to +85 c 48 tqfp-ep* max2106ucm+ 0 c to +85 c 48 tqfp-ep* downloaded from: http:///
max2106 dbs direct downconverter 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc = +4.75v to +5.25v, v fb = +2.4v, c iout_ = c qout_ = 10pf, flclk = 2mhz, rfin_ = unconnected, r iout_ = r qout_ = 10k , v lobufsel = 0.5v, v r fband = v insel = v cpg1 = v cpg2 = +2.4v, v pllin+ = v mod+ = +1.3v, v pllin- = v mod- = +1.1v, t a = +25 ?, unless otherwise noted. typical values are at v cc = +5v, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v to +7v all other pins to gnd................................-0.3v to (v cc + 0.3v) rfin+ to rfin-, tank+ to tank-, idc+ to idc-, qdc+ to qdc- .........................................?v iout_, qout_ to gnd short-circuit duration .......................10s lobuf+/psout+, lobuf-/psout- short-circuit duration..10s continuous current (any pin other than v cc or gnd)........20ma continuous power dissipation (t a = +70 c) 48-pin tqfp-ep (derate 27mw/ c above +70 c) ..........1.5w operating temperature ..........................................0 c to +85 ? junction temperature ......................................................+150 ? storage temperature range .............................-65 c to +150 ? lead temperature (soldering, 10s) .................................+300 ? xtlout output dc voltage 1.9 v rfband input current -200 200 ? 1.44 1.8 2.16 ma 0.48 0.6 0.72 v cpg1 2.4v, v cpg2 2.4v v cpg1 2.4v, v cpg2 0.5v 0.24 0.3 0.36 v cpg1 0.5v, v cpg2 2.4v operating supply current i cc 195 275 ma parameter symbol min typ max units input current i in -15 10 ? input voltage low v il 0.5 v input voltage high v ih 2.4 v flclk input voltage high 1.85 v flclk input voltage low 1.45 v flclk input current (note 1) -1 1 ? operating supply voltage v cc 4.75 5.25 v common-mode input voltage v cmi 1.08 1.2 1.32 v input voltage low -100 mv input voltage high 100 mv input current (note 1) -5 5 ? common-mode output voltage v cmo 2.16 2.4 2.64 v output voltage low (note 2) -150 mv output voltage high (note 2) 150 mv prescaler ratio reference divider ratio 88 charge-pump output highmeasured at fb 0.08 0.1 0.12 conditions referenced to v cmi referenced to v cmi r source = 50k , v flclk = 1.65v referenced to v cmo , lobufsel 0.5v referenced to v cmo , lobufsel 0.5v v cpg1 0.5v, v cpg2 0.5v (v mod+ -v mod- ) 200mv, lobufsel 0.5v 32 32 lobufsel 2.4v, lodivsel 0.5v lobufsel 2.4v, lodivsel 2.4v (v mod+ -v mod- ) -200mv, lobufsel 0.5v 22 11 33 33 frequency synthesizer/lo buffer differential digital outputs (lobuf+/psout+, lobuf-/psout-) differential digital inputs (mod+, mod-, pllin+, pllin-) slew-rate-limited digital input (f lclk ) standard digital inputs (insel, cpg1, cpg2, lobufsel, lodivsel) downloaded from: http:///
max2106 dbs direct downconverter _______________________________________________________________________________________ 3 dc electrical characteristics (continued)(v cc = +4.75v to +5.25v, v fb = +2.4v, c iout_ = c qout_ = 10pf, flclk = 2mhz, rfin_ = unconnected, r iout_ = r qout_ = 10k , v lobufsel = 0.5v, v r fband = v insel = v cpg1 = v cpg2 = +2.4v, v pllin+ = v mod+ = +1.3v, v pllin- = v mod- = +1.1v, t a = +25 ?, unless otherwise noted. typical values are at v cc = +5v, unless otherwise noted.) ac electrical characteristics(ic driven single-ended with rfin- ac-terminated in 75 to gnd, v cc = +4.75v to +5.25v, v iout_ = v qout_ = 0.59vp-p, c iout_ = c qout_ = 10pf, lclk = 2mhz, r iout_ = r qout_ = 10k , v lobufsel = 0.5v, v rfband = v insel = v cpg1 = v cpg2 = +2.4v, v pllin+ = v mod+ = +1.3v, v pllin- = v mod- = +1.1v, t a = +25 c, unless otherwise noted. typical values are at v cc = +5v.) v cpg1 0.5v, v cpg2 0.5v v cpg1 0.5v, v cpg2 2.4v conditions -0.12 -0.1 -0.08 charge-pump output lowmeasured at fb -0.36 -0.3 -0.24 units min typ max symbol parameter v cpg1 2.4v, v cpg2 0.5v v cpg1 2.4v, v cpg2 2.4v -0.72 -0.6 -0.48 ma -2.16 -1.8 -1.44 v gc_ = 1v to 4v -50 50 i gc_ input current ? charge-pump output currentmatching positive to negative % measured at fb -5 5 charge-pump output leakage na measured at fb -25 25 offset voltage (note 1) mv differential output voltageswing vp-p r l = 2k differential 1 common-mode output voltage(note 1) v 0.65 0.85 -50 50 charge-pump output currentdrive (note 1) ? measured at cp 100 f rfin_ rfin_ input frequency range mhz conditions nf noise figure db f rfin _ = 1550mhz, v gc1 = 1v, v gc2 adjusted 0.59vp-p baseband level 10.2 units min typ max symbol parameter inferred by quadrature gain and phase-error test 925 2175 dbm rfin_ input power for 0.59vp-pbaseband levels dbm -25 singlecarrier -68 ip3 rfin_ rfin_ input third-order interceptpoint (note 3) dbm p rfin_ = -25dbm per tone 10.5 10.5 11.5 ip2 rfin_ rfin_ input second-order intercept(note 4) dbm p rfin_ = -25dbm per tone, f lo = 951mhz 17 p1 dbout output-referred 1db compressionpoint (note 5) dbv p rfin_ = -40dbm, signals within filter bandwidth 2 analog control inputs (gc1, gc2) baseband outputs (iout+, iout-, qout+, qout-) v gc1 = v gc2 = +4v (min gain) v gc1 = v gc2 = +1v (max gain) f lo = 2175mhz f lo = 1550mhz f lo = 950mhz dbm p rfin_ = -65dbm per tone -30 -29 -26 f lo = 2175mhz f lo = 1550mhz f lo = 950mhz rf front end p rfin_ = -65dbm db 44.8 p rfin_ = -25dbm downloaded from: http:///
max2106 dbs direct downconverter 4 _______________________________________________________________________________________ ac electrical characteristics (continued)(r fin + ic driven single-ended with rfin- ac-terminated in 75 to gnd, v cc = +4.75v to +5.25v, v iout_ = v qout_ = 0.59vp-p, c iout_ = c qout_ = 10pf, f lclk = 2mhz, r iout_ = r qout_ = 10k , v lobufsel = 0.5v, v rfband = v insel = v cpg1 = v cpg2 = +2.4v, v pllin+ = v mod+ = +1.3v, v pllin- = v mod- = +1.1v, t a = +25 c, unless otherwise noted. typical values are at v cc = +5v.) 12.5 f = 925mhz db rfout noise figure (note 10) 5 7 9 f = 925mhz dbm rfout output third-order interceptpoint (note 10) 1.0 f = 1550mhz 2.0 f = 2175mhz 0.5 f = 925mhz db rfin+ to rfout gain (note 10) degrees quadrature phase error includes effects from baseband filters,measured at 125khz baseband 4 db quadrature gain error includes effects from baseband filters, measured at 125khz baseband f flclk = 2.0625mhz, f c = 31.4mhz f flclk = 1.25mhz, f c = 19.3mhz f flclk = 0.5mhz, f c = 8mhz -0.5 0.5 deviation from ideal 7th order,butterworth, up to 0.7 f c db baseband frequency response(note 1) 750 c idc_ = c qdc_ = 0.22? hz baseband highpass -3db frequency(note 1) 23 f in_band = 100hz to 22.5mhz, f out_band = 67.5mhz to 112.5mhz 1.2 db ratio of in-filter-band to out-of-filter-band noise r fin + return loss (note 6) +13 db 10 10 % lpf -3db cutoff-frequencyaccuracy (note 1) -10 10 -5.5 5.5 f rfin_ = 925mhz, z source = 75 83 3 controlled by flclk signal mhz lpf -3db cutoff-frequency range(note 1) 12 925mhz < f < 2175mhz, z load = 75 db rfout return loss (notes 6, 10) 11 f = 2175mhz 11 f = 1550mhz f = 2175mhz f = 1550mhz 50 iout_, qout_ output real impedance (note 1) parameter symbol min typ max units conditions +14 f rfin_ = 2175mhz, z source = 75 41.5 lo 2nd harmonic rejection (note 7) 32 db average level of v iout_ , v qout_ average level of v iout_ , v qout_ lo half harmonic rejection (note 8) db -66 measured at r fin + lo leakage power (notes 6, 9) dbm rfout port (loopthrough) baseband circuits downloaded from: http:///
max2106 dbs direct downconverter _______________________________________________________________________________________ 5 note 1: minimum and maximum values are guaranteed by design and characterization over supply voltage. note 2 driving differential load of 10k || 15pf. note 3: two signals are applied to rfin_ at f lo - 100mhz and f lo - 199mhz. v gc2 = 1v, v gc1 is set so that the baseband out- puts are at 590mvp-p. im products are measured at baseband outputs but are referred to rf inputs. note 4: two signals are applied to rfin_ at 1200mhz and 2150mhz. v gc2 = 1v, v gc1 is set so that the baseband outputs are at 590mvp-p. im products are measured at baseband outputs but are referred to rf inputs. note 5: p rfin_ = -40dbm so that front-end im contributions are minimized. note 6: using l64733/l64734 demo board from lsi logic. note 7: downconverted level, in dbc, of carrier present at f lo 2, f lo = 1180mhz, f vco = 590mhz, v rfband = unconnected (see histogram plots). note 8: downconverted level, in dbc, of carrier present at f o / 2, f lo = 2175mhz, f vco = 1087.5mhz, v rfband = 2.4v. note 9: leakage is dominated by board parasitics. note 10: v cpg1 = v cpg2 = v rfband = v insel = 0.5v, lclk = 0.5mhz. note 11: guaranteed by design and characterization over supply and temperature. note 12: measured at tuned frequency with pll locked. pll loop bandwidth = 3khz. all phase noise measurements assume tankcomponents have a q > 50. ac electrical characteristics (continued)(ic driven single-ended with rfin- ac-terminated in 75 to gnd, v cc = +4.75v to +5.25v, v iout_ = v qout_ = 0.59vp-p, c iout_ = c qout_ = 10pf, lclk = 2mhz, r iout_ = r qout_ = 10k , v lobufsel = 0.5v, v rfband = v insel = v cpg1 = v cpg2 = +2.4v, v pllin+ = v mod+ = +1.3v, v pllin- = v mod- = +1.1v, t a = +25 c, unless otherwise noted. typical values are at v cc = +5v.) local oscillator synthesizer -96 parameter symbol min typ max units at 100khz offset, f lo = 2175mhz dbc/hz lo phase noise (notes 6, 12) -75 at 10khz offset, f lo = 2175mhz 58 0 figure 1 f rfin = 2175mhz db rfin+ to lo input isolation (note 9) -60 590 1180 mhz lo tuning range (note 11) ns 4 7.26 mhz crystal frequency range (note 1) 0.75 1 1.5 load = 10pf || 10k , f xtlout = 6mhz vp-p xtlout output voltage swing at 1khz offset, f lo = 2175mhz mod+, mod- hold time (note 1) t hm 7 figure 1 conditions ns mod+, mod- setup time (note 1) t sum 70 v lobufsel 2.4v, f lo = 925 mhz + 2175mhz v rms lo buffer output voltage (note 1) synthesizer local oscillator downloaded from: http:///
max2106 dbs direct downconverter 6 _______________________________________________________________________________________ name function pin pin description 2 cflt external bypass for internal bias. bypass this pin with a 0.1 f ceramic chip capacitor to gnd. 3 xtl- inverting input to crystal oscillator. consult crystal manufacturer for circuit loading requirements. 4 xtl+ noninverting input to crystal oscillator. consult crystal manufacturer for circuit loading requirements. 5, 9, 10, 16, 40, 41, 46 gnd ground. connect each of these pins to a solid ground plane. use multiple vias to reduce inductancewhere possible. 7 rfin- rf inverting input. bypass rfin- with 47pf capacitor in series with a 75 resistor to gnd. 8 rfin+ rf noninverting input. connect to 75 source with a 47pf ceramic chip capacitor. 11 qdc- baseband offset correction. connect a 0.22? ceramic chip capacitor from qdc- to qdc+ (pin 12). 12 qdc+ baseband offset correction. connect a 0.22? ceramic chip capacitor from qdc+ to qdc- (pin 11). 13 idc- baseband offset correction. connect a 0.22? ceramic chip capacitor from idc- to idc+ (pin 14). 14 idc+ baseband offset correction. connect a 0.22? ceramic chip capacitor from idc+ to idc- (pin 13). 17 rfout buffered rf output. enabled when insel is low. 18 cpg1 charge-pump gain select. high-impedance digital input. sets the charge-pump output scaling. see dc electrical characteristics for available gain settings. 20 xtlout buffered crystal oscillator output 21 cpg2 charge-pump gain select. high-impedance digital input. sets the charge-pump output scaling. see dc electrical characteristics for available gain settings. 22 gc1 gain control input for rf front end. high-impedance analog input, with an input range of +1v to +4v.see ac electrical characteristics for transfer function. 23 gc2 gain control input for baseband signals. high-impedance analog input, with an input range of +1v to+4v. see ac electrical characteristics for transfer function. 24 insel loopthrough mode enable. high-impedance digital input. drive low to enable the rfout buffer and disable the lo converters. drive high for normal tuner operation. 25 flclk baseband filter cutoff adjust. connect to a slew-rate-limited clock source. see ac electrical characteristics for transfer function. 26 rfband rf input band select input. drive high to enable 1680 mhz to 2175 mhz band. leave unconnected toenable 1180 mhz to 1680 mhz band. connect to gnd to enable 925 mhz to 1180 mhz band. 27 qout- baseband quadrature output. connect to inverting input of high-speed adc. 28 qout+ baseband quadrature output. connect to noninverting input of high-speed adc. 30 iout- baseband in-phase output. connect to inverting input of high-speed adc. 31 iout+ baseband in-phase output. connect to noninverting input of high-speed adc. 32 lodivsel lo buffer divider ratio input. drive high to enable divide-by-one lo buffer output. connect to gnd to enable divide-by-two buffer output. 1, 6, 19, 29, 39, 45 v cc v cc power-supply input. connect each pin to a +5v ?% low-noise supply. bypass each v cc pin to the nearest gnd with a ceramic chip capacitor. 15 lobufsel local oscillator buffer select. connect to gnd to select div32/33 prescaler output; connect v cc to div1 to select div2 lo buffer output. 33 mod+ pecl modulus control. a pecl high on mod+ sets the dual-modulus prescaler to divide by 32. a pecllogic low sets the divide ratio to 33. drive with a differential pecl signal in conjunction with mod- (pin 34). downloaded from: http:///
max2106 dbs direct downconverter _______________________________________________________________________________________ 7 pin description (continued) name function pin 34 mod- pecl modulus control. a pecl low on mod- sets the dual-modulus prescaler to divide by 32. apecl logic high sets the divide ratio to 33. drive with a differential pecl signal in conjunction with mod+ (pin 33). 35 pllin+ pecl phase-locked loop input. drive with a differential pecl signal in conjunction with pllin- (pin 36). 37 lobuf+/ psout+ lobufsel = gnd: pecl prescaler output. differential output of the dual-modulus prescaler. used inconjunction with psout-. requires pecl-compatible termination. lobufsel=v cc : 50 lo buffer noninverting output. 36 pllin- pecl phase-locked loop input. drive with a differential pecl signal in conjunction with pllin+ (pin 35) 42 tank- lo tank oscillator input. connect to an external lc tank with varactor tuning. 38 lobuf-/ psout- lobufsel = gnd: pecl prescaler output. differential output of the dual-modulus prescaler. used inconjunction with psout+. requires pecl-compatible termination. lobufsel = v cc : 50 lo buffer inverting output. 43 vrlo lo internal regulator. bypass with a 1000pf ceramic chip capacitor to gnd. 44 tank+ lo tank oscillator input. connect to an external lc tank with varactor tuning. 47 fb feedback input for loop filter 48 cp voltage drive output. control of external charge-pump transistor. 50% mod+,mod- psout+psout- 50% 50%50% t sum t hm figure 1. modulus control timing diagram downloaded from: http:///
max2106 dbs direct downconverter 8 _______________________________________________________________________________________ functional diagram cp cpg1cpg2 pllin+ pllin- xtl+ xtl- mod+ mod- fbxtlout lobufsel lobuf+/psout+ lobuf-/psout- iout+ iout- qout+ qout- rfout rfband tank+ tank- v cc vrlo cflt gnd rfin+ rfin- gc1gc2 flclk insel idc+ idc- qdc+ qdc- max2106 baseband offset correction charge pump /8 x2 90 /32, 33 1, 2 voltage regulator lodivsel downloaded from: http:///
max2106 dbs direct downconverter _______________________________________________________________________________________ 9 48l,tqfp.eps g 1 2 21-0065 package outline,48l tqfp, 7x7x1.0mm ep option package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///
max2106 dbs direct downconverter maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. g 2 2 21-0065 package outline,48l tqfp, 7x7x1.0mm ep option package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///
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